1-mbit (64k x 16) static ram cy7c1021cv26 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05589 rev. ** revised june 22, 2004 features ? temperature range ? automotive: ?40c to 125c ?high speed ?t aa = 15 ns ? optimized voltage range: 2.5v?2.7v ? low active power: 360 mw (max.) ? automatic power-down when deselected ? independent control of upper and lower bits ? cmos for optimum speed/power ? package offered: 44-pin tsop ii functional description the cy7c1021cv26 is a high-performance cmos static ram organized as 65,536 words by 16 bits. this device has an automatic power-down feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 1 through i/o 8 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 9 through i/o 16 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 1 to i/o 8 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 9 to i/o 16 . see the truth table at the end of this data sheet for a complete description of read and write modes. the input/output pins (i/o 1 through i/o 16 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). note: 1. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c. logic block diagram 64k x 16 ram array i/o 1 ?i/o 8 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 a 15 512 x 2048 sense amps data in drivers oe a 2 a 1 i/o 9 ?i/o 16 ce we ble bhe a 8 selection guide cy7c1021cv26-15 maximum access time (ns) 15 maximum operati ng current (ma) 80 maximum cmos standby current (ma) 10
cy7c1021cv26 document #: 38-05589 rev. ** page 2 of 9 pin configuration pin definitions pin name pin number i/o type description a 0 ?a 15 1?5, 18?21, 24?27, 42?44 input address inputs used to select one of the address locations. i/o 1 ?i/o 16 7?10, 13?16, 29?32, 35?38 input/output bidirectional data i/o lines . used as input or output lines depending on operation. nc 22, 23, 28 no connect no connects . this pin is not connected to the die. we 17 input/control write enable input, active low . when selected low, a write is conducted. when selected high, a read is conducted. ce 6 input/control chip enable input, active low . when low, selects the chip. when high, deselects the chip. bhe , ble 39, 40 input/control byte write select inputs, active low . ble controls i/o 8 ?i/o 1 , bhe controls i/o 16 ?i/o 9 . oe 41 input/control output enable, active low . controls the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. v ss 12, 34 ground ground for the device . should be connected to ground of the system. v cc 11, 33 power supply power supply inputs to the device. note: 2. nc pins are not connected on the die. we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 tsop ii -top view 12 13 41 44 43 42 16 15 29 30 v cc a 15 a 14 a 13 a 12 nc a 4 a 3 oe v ss a 5 i/o 16 a 2 ce i/o 3 i/o 1 i/o 2 bhe nc a 1 a 0 18 17 20 19 i/o 4 27 28 25 26 22 21 23 24 nc v ss i/o 7 i/o 5 i/o 6 i/o 8 a 6 a 7 ble v cc i/o 15 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 a 8 a 9 a 10 a 11
cy7c1021cv26 document #: 38-05589 rev. ** page 3 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [3] .... ?0.5v to +4.6v dc voltage applied to outputs in high-z state [3] ......................................?0.5v to v cc +0.5v dc input voltage [3] ................................ ?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .............. .............. ....... >2001v (per mil-std-883, method 3015) latch-up current...................................................... >200 ma operating range range ambient temperature v cc automotive ?40 c to +125 c2.5v?2.7v electrical characteristics over the operating range parameter description test conditions cy7c1021cv26-15 unit min. max. v oh output high voltage v cc = min., i oh = ?1.0 ma 2.3 v v ol output low voltage v cc = min., i ol = 1.0 ma 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [3] ?0.3 0.8 v i ix input load current gnd < v i < v cc ?3 +3 a i oz output leakage current gnd < v i < v cc , output disabled ?3 +3 a i os output short circuit current [4] v cc = max., v out = gnd ?300 ma i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 80 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 15 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 10 ma capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 2.6v 8pf c out output capacitance 8 pf thermal resistance [5] parameter description test conditions 44-lead tsop-ii unit ja thermal resistance (junction to ambient) [5] still air, soldered on a 3 4.5 inch, two-layer printed circuit board 76.92 c/w jc thermal resistance (junction to case) [5] 15.86 c/w notes: 3. v il (min.) = ?2.0v and v ih (max) = v cc + 0.5v for pulse durations of less than 20 ns. 4. not more than one output should be shorted at one time. duration of the short circuit should not exceed 30 seconds. 5. tested initially and after any design or process changes that may affect these parameters.
cy7c1021cv26 document #: 38-05589 rev. ** page 4 of 9 ac test loads and waveforms [6] switching characteristics over the operating range [7] parameter description cy7c1021cv26-15 unit min. max. read cycle t rc read cycle time 15 ns t aa address to data valid 15 ns t oha data hold from address change 3 ns t ace ce low to data valid 15 ns t doe oe low to data valid 7 ns t lzoe oe low to low-z [8] 0 ns t hzoe oe high to high-z [8, 9] 7 ns t lzce ce low to low-z [8] 3 ns t hzce ce high to high-z [8, 9] 7 ns t pu [10] ce low to power-up 0 ns t pd [10] ce high to power-down 15 ns t dbe byte enable to data valid 7 ns t lzbe byte enable to low-z 0 ns t hzbe byte disable to high-z 7 ns write cycle [11] t wc write cycle time 15 ns t sce ce low to write end 10 ns t aw address set-up to write end 10 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 10 ns t sd data set-up to write end 8 ns t hd data hold from write end 0 ns notes: 6. ac characteristics (except high-z) are te sted using the thevenin load shown in figur e (a). high-z characteristics are tested for all speeds using the test load shown in figure (c). 7. test conditions assume signal transition time of 2.6 ns or le ss, timing reference levels of 1.3v, input pulse levels of 0 to 2.6v. 8. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 9. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (d) of ac test loads. transition is measured 500 mv from steady-state voltage. 10. this parameter is guaranteed by design and is not tested. 11. the internal write time of the memory is defined by the overlap of ce low, we low and bhe /ble low. ce , we and bhe /ble must be low to initiate a write, and the transition of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 2.6 v output r2 30 pf including jig and scope r1 1830 ? 1976 ? 2.6v output 5 pf r 317 ? r2 351 ? high-z characteristics: 90% 10% 2.6v gnd 90% 10% all input pulses rise time: 1 v/ns fall time: 1 v/ns (c) (b) (a)
cy7c1021cv26 document #: 38-05589 rev. ** page 5 of 9 t lzwe we high to low-z [8] 3 ns t hzwe we low to high-z [8, 9] 7 ns t bw byte enable to end of write 9 ns switching characteristics over the operating range [7] (continued) parameter description cy7c1021cv26-15 unit min. max. switching waveforms read cycle no. 1 [12, 13] read cycle no. 2 (oe controlled) [13, 14] notes: 12. device is continuously selected. oe , ce , bhe and/or ble = v il . 13. we is high for read cycle. 14. address valid prior to or coincident with ce transition low. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble current i cc i sb
cy7c1021cv26 document #: 38-05589 rev. ** page 6 of 9 write cycle no. 1 (ce controlled) [15, 16] write cycle no. 2 (ble or bhe controlled) notes: 15. data i/o is high-impedance if oe or bhe and/or ble = v ih . 16. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw data i/o address ce we bhe, ble t t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble we ce
cy7c1021cv26 document #: 38-05589 rev. ** page 7 of 9 write cycle no. 3 (we controlled, low) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe truth table ce oe we ble bhe i/o 1 ?i/o 8 i/o 9 ?i/o 16 mode power h x x x x high-z high-z power-down standby (i sb ) l l h l l data out data out read ? all bits active (i cc ) l h data out high-z read ? lower bits only active (i cc ) h l high-z data out read ? upper bits only active (i cc ) l x l l l data in data in write ? all bits active (i cc ) l h data in high-z write ? lower bits only active (i cc ) h l high-z data in write ? upper bits only active (i cc ) l h h x x high-z high-z selected, outputs disabled active (i cc ) l x x h h high-z high-z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package name package type operating range 15 CY7C1021CV26-15ZE z44 44-lead tsop type ii automotive
cy7c1021cv26 document #: 38-05589 rev. ** page 8 of 9 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all products and company names mentioned in this doc ument are the trademarks of their respective holders. package diagrams 44-pin tsop ii z44 51-85087-*a
cy7c1021cv26 document #: 38-05589 rev. ** page 9 of 9 document history page document title: cy7c1021cv26 1-mbit (64k x 16) static ram document number: 38-05589 rev. ecn no. issue date orig. of change description of change ** 238454 see ecn rkf new datasheet for automotive
|
